AS7038RB datasheet(110/127 Pages) AMSOSRAM

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AS7038RB

Functional Description

Datasheet

• PUBLIC

DS000726

• v2-00 • 2021-Jun-02

126

│ 109

I²C Page Write: Shows the format of an I²C page write access

The transmission begins with the START condition, which is generated by the master when the bus is

in IDLE state (the bus is free). The device-write address is followed by the word address. After the

word address any number of data bytes can be sent to the slave. The word address is incremented

internally, in order to write subsequent data bytes on subsequent address locations.

For reading data from the slave device, the master has to change the transfer direction. This can be

done either with a repeated START condition followed by the device-read address, or simply with a

new transmission START followed by the device-read address, when the bus is in IDLE state. The

device-read address is always followed by the 1st register byte transmitted from the slave. In Read

mode any number of subsequent register bytes can be read from the slave. The word address is

incremented internally.

Figure 149:

I²C Random Read

I²C Random Read: Shows the format of an I²C random read access

Random Read and Sequential Read are combined formats. The repeated START condition is used to

change the direction after the data transfer from the master.

The word address transfer is initiated with a START condition issued by the master while the bus is

idle. The START condition is followed by the device-write address and the word address.

In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after

the acknowledge bit of the word address transfer. After the reception of the device-read address, the

slave becomes the transmitter. In this state the slave transmits register data located by the previous

received word address vector. The master responds to the data byte with a not-acknowledge, and

issues a STOP condition on the bus.

Figure 150:

I²C Sequential Read

read register

WA++

data

WA++

read register

WA++

data

WA++

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