Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 13MHz Reference Clock

SMSC USB3318

5

Revision 1.3 (11-02-07)

PRODUCT PREVIEW

3

VBAT

Power

N/A

Regulator input. The regulator supply can

be from 5.5V to 3.1V.

4

VDD3.3

Power

N/A

3.3V Regulator Output. A 2.2uF (<1 ohm

ESR) bypass capacitor to ground is

required for regulator stability. The

bypass capacitor should be placed as

close as possible to the USB3318.

5

DM

I/O,

Analog

N/A

D- pin of the USB cable.

6

DP

I/O,

Analog

N/A

D+ pin of the USB cable.

7

CPEN

Output,

CMOS

High

External 5 volt supply enable. This pin is

used to enable the external Vbus power

supply. The CPEN pin is low on POR.

This pad uses VDD3.3 logic level.

8

DATA[7]

I/O,

CMOS

N/A

ULPI bi-directional data bus. DATA[7] is

the MSB.

9

DATA[6]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

10

DATA[5

I/O,

CMOS

N/A

ULPI bi-directional data bus.

11

DATA[4]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

12

CLKOUT

Output,

CMOS

N/A

60MHz reference clock output. All ULPI

signals are driven synchronous to the

rising edge of this clock.

13

DATA[3]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

14

DATA[2]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

15

DATA[1]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

16

DATA[0]

I/O,

CMOS

N/A

ULPI bi-directional data bus. DATA[0] is

the LSB.

17

VDDIO

Power

N/A

1.8V to 3.3V ULPI interface supply

voltage. This voltage sets the value of

18

NXT

Output,

CMOS

High

The PHY asserts NXT to throttle the data.

When the Link is sending data to the

PHY, NXT indicates when the current

byte has been accepted by the PHY. The

Link places the next byte on the data bus

in the following clock cycle.

Table 1 USB3318 Pin Description (continued)