MNSC140CORESLASHD datasheet(45/104 Pages) FREESCALE

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Clock Configuration

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

2-5

2.5.2.1 System Clock Control Register

SCCR is memory-mapped into the SIU register map of the MSC8103.

2.5.2.2 System Clock Mode Register

SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control

signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. For

details of the available setting options, see AN2306/D.

Bit

—

Type

Reserved

Reset

—

Bit

1617

1819

2021

2223

2425

262728293031

—

CLKODIS

—DFBRG

Type

Reserved

R/W

Reserved

R/W

Reset

—

Figure 2-2.

System Clock Control Register (SCCR)—0x10C80

Table 2-7.

SCCR Bit Descriptions

Name

Bit No.

Defaults

Description

Settings

PORESET

Hard Reset

—

0–26

—

Reserved. Write to 0 fro future compatibility.

CLKODIS

Unaffected

CLKOUT Disable

Disables the CLKOUT signal. The value of

CLKOUT when disabled is indeterminate (can be 1

or 0).

CLKOUT enabled (default)

CLKOUT disabled

—

28–29

—

Reserved. Write to 0 fro future compatibility.

DFBRG

30–31

Unaffected

Division Factor for the BRG Clock Defines the

BRGCLK frequency. Changing this value does not

result in a loss of lock condition.

Divide by 4

Divide by 16 (default value)

Divide by 64

Divide by 256

Bit

COREPDF

COREMF

BUSDF

CPMDF

Type

Reset

—

Bit

1617

1819

2021

2223

2425

262728293031

SPLLPDF

SPLLMF

—

DLLDIS

—

COREDF

Type

Reset

—

Figure 2-3.

System Clock Mode Register (SCMR)—0x10C88

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