MSC8103 datasheet(49/104 Pages) FREESCALE

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AC Timings

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

2-9

2.6.4

Reset Timing

The MSC8103 has several inputs to the reset logic:

• Power-on reset (PORESET)

• External hard reset (HRESET)

• External soft reset (SRESET)

Asserting an external PORESET causes concurrent assertion of an internal PORESET signal, HRESET, and SRESET.

When the external PORESET signal is deasserted, the MSC8103 samples several configuration pins:

• RSTCONF—determines whether the MSC8103 is a master (0) or slave (1) device

• DBREQ—determines whether to operate in normal mode (0) or invoke the SC140 debug mode (1)

• HPE—disable (0) or enable (1) the host port (HDI16)

• BTM[0–1]—boot from external memory (00) or the HDI16 (01)

All these reset sources are fed into the reset controller, which takes different actions depending on the source of the

reset. The reset status register indicates the last sources to cause a reset. Table 2-12 describes reset causes.

Table 2-11.

Clock Ranges

Clock

Symbol

Maximum Rated Core Frequency

All

Max. Values for SC140 Clock Rating of:

Min

275 MHz

300 MHz

Input Clock

CLKIN

18 MHz

91.67 MHz

100 MHz

SPLL MF Clock

SPLLMFCLK

18 MHz

34.38 MHz

37.5 MHz

Bus/Output

BCLK

CLKOUT

18 MHz

91.67 MHz

100 MHz

Serial Communications Controller

SCLK

35 MHz

91.67 MHz

100 MHz

Communications Processor Module

CPMCLK

70 MHz

183.3 MHz

200 MHz

SC140 Core

DSPCLK

72 MHz

275 MHz

300 MHz

Baud Rate Generator

•

For BRG DF = 4

•

For BRG DF = 16 (default)

•

For BRG DF = 64

•

For BRG DF = 256

BRGCLK

36 MHz

9 MHz

2.25 MHz

562.5 KHz

91.67 MHz

22.91 MHz

5.73 MHz

1.43 MHz

100 MHz

25 MHz

6.25 MHz

1.56 MHz

Table 2-12.

Reset Causes

Name

Direction

Description

Power-on reset

(PORESET)

Input

PORESET initiates the power-on reset flow that resets all the MSC8103s and configures

various attributes of the MSC8103, including its clock mode.

Hard reset

(HRESET)

Input/Output

The MSC8103 can detect an external assertion of HRESET only if it occurs while the

MSC8103 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open-

drain pin.

Soft reset

(SRESET)

Input/Output

The MSC8103 can detect an external assertion of SRESET only if it occurs while the

MSC8103 is not asserting reset. SRESET is an open-drain pin.

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