X9C102, X9C103, X9C104, X9C503

FN8222 Rev 4.00

Page 8 of 12

Jan 11, 2019

Basic Configurations of Electronic Potentiometers

Basic Circuits

VR

VR

I

THREE TERMINAL POTENTIOMETER;

VARIABLE VOLTAGE DIVIDER

TWO TERMINAL VARIABLE RESISTOR;

VARIABLE CURRENT

VH/RH

VL/RL

VW/RW

CASCADING TECHNIQUES

BUFFERED REFERENCE VOLTAGE

–

+

+5V

R1

+V

-5V

VW

VREF

VOUT

OP-07

VW/RW

VW/RW

+V

+V

+V

X

(a)

(b)

VOUT = VW/RW

NONINVERTING AMPLIFIER

VO = (1+R2/R1)VS

VOLTAGE REGULATOR

R1

R2

Iadj

VO (REG) = 1.25V (1+R2/R1)+Iadj R2

VO (REG)

VIN

317

OFFSET VOLTAGE ADJUSTMENT

+

–

VS

VO

R2

R1

100k



10k



10k



10k



-12V

+12V

TL072

COMPARATOR WITH HYSTERESIS

VUL = {R1/(R1 + R2)} VO(MAX)

VLL = {R1/(R1 + R2)} VO(MIN)

+

–

VS

VO

R2

R1

LM308A

+5V

-5V

+

–

VS

VO

R2

R1

LT311A

(FOR ADDITIONAL CIRCUITS SEE AN1145)

Revision History

Rev.

Date

Description

4.00

Jan 11, 2019

Updated Ordering Information table to remove Obsolete and Retired parts.

Added Revision History.

Updated PODs for X9C102, X9C104, and X9C503 SOICs from: MDP0027 to: M8.15E and X9C103 SOIC from:

MDP0027 to: M8.15, to include the Land Pattern design and convert dimensions from table to graphics.

Updated Intersil disclaimer to Renesas disclaimer.