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APEX20KC Folha de dados(PDF) 85 Page - Altera Corporation |
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APEX20KC Folha de dados(HTML) 85 Page - Altera Corporation |
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85 / 90 page ![]() Altera Corporation 85 APEX 20KC Programmable Logic Device Data Sheet Tables 68 and 69 show selectable I/O standard input and output delays for APEX 20KC devices. If you select an I/O standard input or output delay other than LVCMOS, add the delay for the selected speed grade to the LVCMOS value. Table 67. EP20K1000C External Bidirectional Timing Parameters Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit Min Max Min Max Min Max tINSUBIDIR 1.86 2.54 3.15 ns tINHBIDIR 0.00 0.00 0.00 ns tOUTCOBIDIR 2.00 4.63 2.00 5.26 2.00 5.69 ns tXZBIDIR 8.98 9.89 10.67 ns tZXBIDIR 8.98 9.89 10.67 ns tINSUBIDIRPLL 4.17 5.27 - ns tINHBIDIRPLL 0.00 0.00 - ns tOUTCOBIDIRPLL 0.50 2.32 0.50 2.55 - - ns tXZBIDIRPLL 6.67 7.18 - ns tZXBIDIRPLL 6.67 7.18 - ns Table 68. Selectable I/O Standard Input Delays Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit Min Max Min Max Min Max Min LVCMOS 0.00 0.00 0.00 ns LVTTL 0.00 0.00 0.00 ns 2.5 V 0.00 0.00 0.00 ns 1.8 V 0.04 0.11 0.14 ns PCI 0.00 0.04 0.03 ns GTL+ –0.30 0.25 0.23 ns SSTL-3 Class I –0.19 –0.13 –0.13 ns SSTL-3 Class II –0.19 –0.13 –0.13 ns SSTL-2 Class I –0.19 –0.13 –0.13 ns SSTL-2 Class II –0.19 –0.13 –0.13 ns LVDS –0.19 –0.17 –0.16 ns CTT 0.00 0.00 0.00 ns AGP 0.00 0.00 0.00 ns |
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