6.42

7133SA/LA, 7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

9

Jun.16.21

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(5)

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5)

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no

relationship to valid output data.

4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.

5. R/W = VIH, and the address is valid prior to or coincidental with CE transition LOW.

2746 drw 07

tAA

tOH

tOH

DATAOUT

ADDRESS

tRC

DATA VALID

PREVIOUS DATA VALID

BUSYOUT

tBDD

(3,4)

2746 drw 08

tAOE

tLZ

tHZ

DATAOUT

CE

tACE

VALID DATA

OE

CURRENT

ICC

ISB

tPU

50%

tLZ

tPD

50%

tHZ

(1)

(4)

(1)

(4)

(2)

(2)