6.42

7133SA/LA, 7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

13

Jun.16.21

2746 drw 11

tDW

tAPS

ADDR"A"

tWC

MATCH

tWP

R/

W"A"

DATAIN"A"

ADDR"B"

tDH

VALID

(1)

MATCH

BUSY"B"

tBDA

VALID

tBDD

tDDD

(4)

tWDD

DATAOUT "B"

Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3)

Timing Waveform of Write with BUSY(3)

NOTES:

1. tWH must be met for both BUSY input (IDT7143, slave) and output (IDT7133, master).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

NOTES:

1. To ensure that the earlier of the two ports wins, tAPS is ignored for Slave (IDT7143).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

2746 drw 12

R/

W"A"

BUSY"B"

tWP

tWB

R/

W"B"

tWH

(1)

(2)

,