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M25P05-AVMP6P Folha de dados(PDF) 25 Page - Numonyx B.V |
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M25P05-AVMP6P Folha de dados(HTML) 25 Page - Numonyx B.V |
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25 / 52 page ![]() M25P05-A Instructions 25/52 Table 7. Protection modes W signal SRWD bit Mode Write protection of the status register Memory content Protected area(1) 1. As defined by the values in the block protect (BP1, BP0) bits of the status register, as shown in Table 2. Unprotected area(1) 10 Software protected (SPM) Status register is writable (if the WREN instruction has set the WEL bit). The values in the SRWD, BP1 and BP0 bits can be changed Protected against page program, sector erase and bulk erase Ready to accept page program and sector erase instructions 00 11 01 Hardware protected (HPM) Status register is hardware write protected. The values in the SRWD BP1 and BP0 bits cannot be changed Protected against page program, sector erase and bulk erase Ready to accept page program and sector erase instructions |
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