CY28331
Document #: 38-07491 Rev. *E
Page 13 of 17
USB, 24_48 Clock Outputs
VOL
Output Low Voltage
IOL = 9.0 mA
0.4
V
VOH
Output High Voltage
IOH = –12.0 mA
2.4
V
IOL
Output Low Current
VO = 0.8V
16
mA
IOH
Output High Current
VO = 2.0V
–22
mA
F33
Frequency Actual
24.004
MHz
F66
48.008
MHz
tR
Output Rise Edge Rate
Measured from 20% to 80%
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 80% to 20%
0.5
2
V/ns
tD
Duty Cycle
Measured at 1.5V
45
55
%
TCCJ
24_48MHz Cycle-to-Cycle Jitter
Measured at 1.5V
0
250
500
ps
TCCJ
USB Cycle-to-Cycle Jitter
Measured at 1.5V
0
200
ps
TLTJ
Long-term Jitter
Measured at 1.5V
–1000
1000
ps
TSTABLE
Frequency Stabilization from
Power-up
Measure from full supply voltage
0
3
ms
RON
Output Impedance
Average value during switching transition
20
24
60
W
Table 6. Skew [2]
Parameter
Description
Conditions
Skew Window Unit
TSK_CPU_CPU
CPU to CPU skew, time independent Measured @ crossing points for CPUT rising
edges1
250
ps
TSK_CPU_PCI33
CPU to PCI33 skew, time
independent
Measured @ crossing points for CPUT rising
edge and 1.5V PCI clocks
500
ps
TSK_PCI33_PCI33
PCI33 to PCI33 skew, time
independent
Measured between rising @ 1.5V
500
ps
TSK_PCI33_HT66
PCI33 to HT66 skew, time
independent
Measured between rising @ 1.5V
500
ps
TSK_CPU_HT66
CPU to HT66 skew, time
independent
Measured @ crossing points for CPUT rising
edge and 1.5V for HyperTransport clocks
500
ps
TSK_HT66_HT66
HT66 to HT66 skew, time
independent
Measured between rising @ 1.5V
500
ps
TSK_CPU_CPU
CPU to CPU skew, time variant
Measured @ crossing points for CPUT rising
edges
200
ps
TSK_CPU_PCI33
CPU to PCI33 skew, time variant
Measured @ crossing points for CPUT rising
edge and 1.5V PCI clocks
200
ps
TSK_PCI33_PCI33
PCI33 to PCI33 skew, time variant
Measured between rising @ 1.5V
200
ps
TSK_PCI33_HT66
PCI33 to HT66 skew, time variant
Measured between rising @ 1.5V
200
ps
TSK_CPU_HT66
CPU to HT66 skew, time variant
Measured @ crossing points for CPUT rising
edge and 1.5V for HyperTransport clocks
200
ps
TSK_HT66_HT66
HT66 to HT66 skew, time variant
Measured between rising @ 1.5V
200
ps
Note:
2. All skews in this skew budget are measured from the first referenced signal to the next. Therefore, this skew specifies the maximum SKEW WINDOW between
these two signals to be 500 ps whether the CPU crossing leads or lags the PCI clock. This should NOT be interpreted to mean that the PCI33 edge could either
be 500 ps before the CPU clock to 500 ps after the clock, thus defining a 1000ps window in which the PCI33 clock edge could fall.
AC Electrical Specifications (continued)
Parameter
Description
Test Condition
PCI133_HT66 = 66MHz
Min.
Typ.
Max.
Unit
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