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MediaClock™
Mini Disc Clock Generator
CY24115
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07275 Rev. *C
Revised August 10, 2004
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• 3.3V operation
• 8-pin SOIC package
Benefits
• High-performance PLL tailored for mini disc applica-
tions
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
• Industry standard package saves on board space
Part Number Outputs
Input Frequency Range
Output Frequencies
CY24115-1
1
1 MHz–30 MHz
45.1584 MHz/90.3168 MHz (selectable)
CY24115-2
1
1 MHz–30 MHz
90.3168 MHz/180.6336 MHz (selectable)
Logic Block Diagram
XIN
XOUT
OUTPUT
DIVIDERS
PLL
OSC
FS0
Q
P
VCO
VDD
VSS
Φ
CLKA
FS1
CLKSEL
8-pin SOIC
CY24115
Pin Configurations
1
2
3
4
XOUT
XIN
CLKSEL
CLKA
VSS
FS1
FS0
5
6
7
8
VDD
Table 1. CLKSEL Function CY24115-1
CLKSEL
CLKA
Unit
PPM Error
0
45.1584
MHz
0
1
90.3168
MHz
0
Table 2. CLKSEL Function, CY24115-2
CLKSEL
CLKA
Unit
PPM Error
0
90.3168
MHz
0
1
180.6336
MHz
0
Table 3. Input Frequency Function, CY24115-1 and CY24115-2
FS1
FS0
Xtal Input
Unit
0
0
2.8224
MHz
0
1
5.6448
MHz
1
0
11.2896
MHz
1
1
22.5792
MHz
FREQUENCY
TABLE
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