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ISL54053_0709 Folha de dados(PDF) 5 Page - Intersil Corporation

Nome de Peças ISL54053_0709
Descrição Electrónicos  Ultra Low ON-Resistance, Low Voltage, Single Supply, SPDT Analog Switch
PDF  11 Pages
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL54053_0709 Folha de dados(HTML) 5 Page - Intersil Corporation

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5
FN6460.2
September 25, 2007
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 4),
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 5, 6)
TYP
MAX
(Notes 5, 6) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Full
0
-
V+
V
ON-Resistance, rON
V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0V to V+,
(See Figure 5)
25
-
2.33
-
Ω
Full
-
2.54
-
Ω
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
25
-
68
-
ns
Full
-
93
-
ns
Turn-OFF Time, tOFF
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
25
-
45
-
ns
Full
-
71
-
ns
Break-Before-Make Time Delay, tD
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 3, Note 8)
Full
-
15
-
ns
Charge Injection, Q
VG = 0, RG = 0Ω, CL = 1.0nF (See Figure 2)
25
-
18
-
pC
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
-
0.4
V
Input Voltage High, VINH
Full
1
-
-
V
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
50%
tr < 20ns
tf < 20ns
tOFF
90%
VINH
0V
VNx
VINL
tON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOUT
V
OUT
V
(NO or NC)
R
L
R
L
r
ON
()
+
----------------------------
=
SWITCH
INPUT
LOGIC
INPUT
VOUT
RL
CL
COM
NO OR NC
IN
50
Ω
35pF
GND
V+
C
ISL54053



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