LAN8808D datasheet(54/80 Pages) MICROCHIP

54 / 80 page

LAN8808D

DS00005833C-page 54

• Variable I/O Power Supply (on VDDIO) set for ~1.5V (typical)

The POR circuits have a “dead zone” between bottom range of valid operational voltage and where POR trips (e.g., -

15%/20%). The Over/Under Voltage Protection enables tightening this range to just under the bottom of the supply

range.

5.20

JTAG

An IEEE 1149.1 compliant TAP Controller supports boundary scan and various test modes.

The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface consists of four

pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array and an instruction register. The JTAG

pins are described in Table 3-6. The JTAG interface conforms to the IEEE Standard 1149.1 - 2001 Standard Test Access

Port (TAP) and Boundary-Scan Architecture.

All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI are clocked into

the test logic on the rising edge of TCK, while the output signal TDO is clocked on the falling edge.

JTAG pins are multiplexed with the GPIO pins. The JTAG functionality is selected when the TESTMODE pin is asserted.

The implemented JTAG instructions and their OP Codes are shown in Table 5-11. JTAG timing information is provided

in Section 6.6.6, "JTAG Timing".

TABLE 5-11:

JTAG OP CODES

Instruction

OP Code

CLAMP

4’b0000

EXTEST

4’b0001

(RESERVED)

4’b0010

(RESERVED)

4’b0011

INTEST

4’b0100

SAMPLE_PRELOAD

4’b0101

HIGHZ

4’b0110

HOST-IJTAG ACCESS

4’b0111

ID CODE

4’b1000

BYPASS

4’b1001 to 4’b1111

Note:

The JTAG device ID is 00381445h.

Note:

All digital I/O pins support IEEE 1149.1 operation. Analog pins do not support IEEE 1149.1 operation.

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