CLC016MTC datasheet(9/19 Pages) NSC

9 / 19 page

Product Description (Continued)

ence is detected, FD requests the ARS block to start a

search to match the rate. Once the PLL acquires phase lock,

the PLL takes control and the FD goes inactive.

Phase Detector (PD)

The PD compares the phase of the VCO to the phase of the

input data. The PD output is a differential current which is

proportional to the phase error. The PD gain has units of

amperes per radian and is dependent upon the data transi-

tion density (

ρ). The data transition density is defined as the

average number of data transitions per clock cycle, and is

bounded by 0

≤ρ≤ 1. The PD output is connected to the

VCO through the external loop filter network. This network

translates the PD output current to a voltage that controls the

VCO.

Loop Filter (LF)

The external Loop Filter shown in Figure 3 is made up of

passive components R

BW,CZ, and CP. This external loop

filter controls the PLL dynamics and acquisition time.

The Frequency Detector supplies its signal to the C

Z capaci-

tor, and takes control of the VCO under the condition of

frequency unlock. The selection of the filter components is

covered in the Loop Filter Design section.

Voltage Controlled Oscillator (VCO)

The VCO is a temperature-compensated, factory-trimmed

multivibrator that requires no external capacitors for tuning. It

is stable over temperature and power supply variations. This

eliminates the need for potentiometers to adjust each of the

VCO center frequencies to correspond with the input data

rates. Instead, an external resistor (R

n) is used to set each of

four data rates in the range of 40 Mbps to 400 Mbps.

Carrier Detector (CD)

The CD circuit is a retriggerable one-shot which retriggers on

every data transition. When data transitions occur at a rate

≥1 transition per µs, CD indicates the presence of data at the

input pins DDI and DDI. CD also inputs a signal to ARS that

inhibits any rate search from occurring in the absence of

input data. When CD in connected to the MUTE pin, and no

data is present, the output clock (SCO, SCO) and data

(SDO, SDO) lines are latched.

Auto-Rate Select (ARS) and Multiplexer (MUX)

The ARS, in conjunction with the MUX, sequences through

the user-configured resistor values (R

n) in an unlocked con-

dition. The ARS has two modes: Auto-Rate Mode (ARM) and

Manual-Rate Mode (MRM). It incorporates additional fea-

tures and functions that are discussed in the section named

Auto-Rate Selection.

When ARS is in Auto-Rate Mode, its inputs are the FD (the

LHP control line), the Carrier Detect (CD), the VCO (CLK),

and Latched Data output. These input signals produce an

external Search (SER) signal that, when connected to the

ACQ/WR input, enables the ARM operation. A single capaci-

tor, C

ARS, sets the ARM sequence time for stepping through

the different user-configured data rates.

The timing section of the ARS block controls the digital input

analog multiplexer (MUX). Under the control of ARS, the

MUX steps through each data rate starting with the

previously-selected resistor R

n and incrementing to Rn+1,

etc. in order of R

0,R 1,R2,R3,R0, .... This sequence is

repeated until lock is achieved. The 2-bit bidirectional bus,

comprised of RD0 and RD1, indicates the selected data rate.

The RD0, RD1 bidirectional bus is set to output mode when

AUTO is active (high). Therefore, RD0, RD1 can be moni-

tored when AUTO is active. When no data is present at the

inputs, CD will inhibit the ARM.

In manual mode the RD0, RD1 lines are set to input mode.

Therefore, RD0, RD1 cannot be monitored when AUTO is

inactive. The selection of external components for both

modes of operation is discussed in sections, Resistor Se-

lection for Data Rates, and Auto-Rate Selection.

DESIGN GUIDELINES

Resistor Selection for Data Rates

The CLC016 Data Retiming PPL supports 4 different data

rates using user-selected resistors that set the VCO center

frequency. The resistors found in Figures 1, 2 are identified

by the reference designators R

n, where n is 0, 1, 2 and 3.

It is recommended that the user select resistor values with

tolerances of 1% and temperature coefficients of

≤100 ppm/

˚C. Refer to Table 1 and Table 2 for calculated resistor

values for SMPTE and SONET standards. Resistors for

other data rates are determined from the following equation:

wheren=0,1,2,3and f

CLK is the desired data rate.

TABLE 1. Resistor Values for SMPTE 259M Data Rates

Data Rate

(Mbps)

Ref. Des.

(in Figures

1, 2)

Calculated

Resistor

Ω)

Resistors

(in Figures

1, 2)

Ω)

143

6.79

6.81

177

5.45

5.49

270

3.50

3.48

360

2.58

2.55

TABLE 2. DS-3 and SONET/SDH Resistor Values

Data Rate

(Mbps)

Calculated

Resistor

Ω)

1% Resistors

Ω)

44.7

22.1

51.84

19.1

155.52

6.23

6.19

311.04

3.02

3.01

Loop Filter Design

The function of the PLL is to low-pass filter the jitter of the

incoming data stream. The jitter transfer function for the PLL

(or the phase transfer function) is set by the phase detector

gain, the loop filter transfer function, and the VCO gain.

These elements are shown in the small-signal block dia-

gram, Figure 4.

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