CLC016 datasheet(11/19 Pages) NSC

11 / 19 page

Product Description (Continued)

As an example, assume that the amount of jitter peaking that

can be tolerated is 0.05 dB. From the jitter peaking design

equation (or from Figure 6) the required value of

α is:

α . 0.05[0.134 + (0.058)(0.05)] = 0.007

Now assuming that the loop bandwidth is 644 kHz and that

the value of R

BW is 500

Ω, the value of C

Z is:

The value of C

Z also affects the acquisition performance of

the PLL. Estimate the acquisition time with the following

equation:

where t

ACQ xfCLK is the acquisition time in number of bit

cells.

Selecting C

Capacitor C

P establishes a high frequency pole in the loop

filter to remove high frequency spectral components from the

phase detector. The pole frequency f

P is:

In general, the pole should be set at least a factor of 4 above

the PLL bandwidth, f

BW. Therefore, select CP using:

For example, if R

BW is 500

Ω and f

BW is 644 kHz, then an

appropriate value for C

P is:

Choosing a value for C

P larger than the value recommended

by the selection equation will introduce jitter peaking. Reduc-

ing the value of C

P below that recommended by the selec-

tion equation is acceptable, but will result in some increase

in jitter. This is most noticeable with large fractional loop

bandwidths.

In addition, C

P can affect the ability of the PLL to acquire

lock, especially at high data rates. Because of this, it is

recommended to eliminate C

P entirely for the condition of

high data rate (>300 Mbps) combined with narrow loop

bandwidth (<0.1%).

Multiple Rate Considerations

BW establishes the fractional loop bandwidth. For a fixed

value of R

BW,fBW will vary with the selected data rate. The

location of the critical frequencies f

Z and f P, however, are

independent of data rate.

To control jitter peaking for all multi-rate application choose:

•

the value of C

Z for the smallest value of fBW (which is

obtained at the lowest data rate).

•

the value of C

P for the largest value of fBW (which is

obtained at the highest data rate).

Loop Filter Element Summary Table

The table below summarizes the recommended loop filter

element values for each of the four SMPTE 259M data rates

and a fractional loop bandwidth of 0.25%. The final row of

the table gives the recommended values for the multi-rate

case, where all four of the SMPTE rates are configured.

Data Rate

(Mbps)

(kHz)

(

Ω)

(µF)

(pF)

143

358

500

0.10

200

177

443

500

0.10

160

270

675

500

0.047

100

360

900

500

0.04

143–360

0.25% f

CLK

500

0.10

Component Types and Tolerances

It is recommended that R

BW resistors have tolerances of 1%

and temperature coefficients of

≤100 ppm/˚C. The recom-

mended capacitors are ceramic surface mount with 5% tol-

erance or better.

AUTO-RATE SELECTION

Auto Rate Mode (ARM)

This section provides more detail on the ARS sub-system

and how to use it. Figure 7 shows a detailed view of the ARS

portion of the Figure 3 block diagram

The auto-rate mode is enabled by connecting AUTO to V

and SER to ACQ/WR through the 1 k

Ω/1 nF network. When

the VCO is not at the input data rate, SER goes high en-

abling the ARS oscillator and the Latch. The oscillator incre-

ments the 2-bit counter and causes the VCO to sequence

through the rates determined by resistor R

n (beginning at the

currently selected rate and advancing the index, n, upward).

The oscillator period (T

ARS) is determined by CARS. When

the VCO rate is at the input data rate, SER goes low and

ceases to increment the counter.

10008718

FIGURE 6. Jitter Peaking Curve

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