LTC1065 datasheet(13/20 Pages) AD

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LTC1066-1

10661fa

–26

–85

INPUT FREQUENCY

1066-1 F07

fCLK – fC

2fCLK – fC

2fCLK – 4fC

fCLK – 4fC

fCLK + 4fC

2fCLK + 4fC

fCLK + fC

2fCLK + fC

fCLK

2fCLK

–60

–80

INPUT FREQUENCY

1066-1 F06

fCLK – fC

2fCLK – fC

2fCLK – 2.3fC

2fCLK + 2.3fC

fCLK + fC

2fCLK + fC

fCLK

2fCLK

APPLICATIONS INFORMATION

Aliasing

In a sampled-data system the sampling theorem says that

if an input signal has any frequency components greater

than one half the sampling frequency, aliasing errors will

appear at the output. In practice, aliasing is not always a

serious problem. High order switched-capacitor lowpass

filters are inherently band limited and significant aliasing

occurs only for input signals centered around the clock

frequency and its multiples.

Figure 6 shows the LTC1066-1 aliasing response when

operated with a clock-to-cutoff frequency ratio of 50:1.

With a 50:1 ratio LTC1066-1 samples its input twice

during one clock period and the sampling frequency is

equal to two times the clock frequency.

The figure also shows the maximum aliased output gener-

ated for inputs in the range of 2fCLK ±fC. For instance, if the

LTC1066-1 is programmed to produce a cutoff frequency

of 20kHz with 1MHz clock, a 10mV, 1.02MHz input signal

will cause a 10

µV aliased signal at 20kHz. This signal will

be buried in the noise. Maximum aliasing will occur only

for input signals in the narrow range of 2MHz

±20kHz or

multiples of 2MHz.

Figure 7 shows the LTC1066-1 aliased response when

operated with a clock-to-cutoff frequency ratio of 100:1

(linear phase response with pin 8 to ground).

Figure 6. Aliasing vs Frequency

fCLK/fC = 50:1 (Pin 8 to V

Clock is a 50% Duty Cycle Square Wave

Figure 7. Aliasing vs Frequency

fCLK/fC = 100:1 (Pin 8 to Ground)

Clock is a 50% Duty Cycle Square Wave

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