CY28RS400 datasheet(10/18 Pages) SPECTRALINEAR

10 / 18 page

CY28RS400

Rev 1.0, November 22, 2006

Page 10 of 18

CPU_STP# Assertion

The CPU_STP# signal is an active low input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

When the CPU_STP# pin is asserted, all CPU outputs that are

set with the SMBus configuration to be stoppable via assertion

of CPU_STP# will be stopped within two–six CPU clock

periods after being sampled by two rising edges of the internal

CPUC clock. The final states of the stopped CPU signals are

CPUT = HIGH and CPUC = LOW. There is no change to the

output drive current values during the stopped state. The

CPUT is driven HIGH with a current value equal to 6 x (Iref),

and the CPUC signal will be Hi-Z. When the control register

CPU_STP Hi-Z bit corresponding to the output of interest is

programmed to ‘1’, the final state of the stopped CPU clock is

low (due to external 50 ohm pull-down resistor), both CPUT

clock and CPUC clock outputs will not be driven.

CPU_STP# Deassertion

The deassertion of the CPU_STP# signal will cause all CPU

outputs that were stopped to resume normal operation in a

synchronous manner. Synchronous manner meaning that no

short or stretched clock pulses will be produce when the clock

resumes. The maximum latency from the deassertion to active

outputs is 2 - 6 CPU clock cycles.

Figure 4. Power-down Deassertion Timing Waveform

DOT96C

CPUC, 133MHz

CPUT, 133MHz

SRCC 100MHz

USB, 48MHz

DOT96T

SRCT 100MHz

Tstable

<1.8nS

PCI, 33MHz

REF

Tdrive_PWRDN#

<300 S, >200mV

CPU_STP#

CPUT

CPUC

Figure 5. CPU_STP# Assertion Waveform

CPU_STP#

CPUT

CPUC

CPUT Internal

Tdrive_CPU_STP#,10nS>200mV

CPUC Internal

Figure 6. CPU_STP# Deassertion Waveform

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