ADE7166ASTZF8 datasheet(26/144 Pages) AD

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ADE7566/ADE7569/ADE7166/ADE7169

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Table 17. Power Management Interrupt Flag SFR (IPSMF, 0xF8)

Bit

Address

Mnemonic

Default

Description

0xFF

FPSR

Power Supply Restored Interrupt Flag. Set when the VDD power supply has been restored.

This occurs when the source of VSWOUT changes from VBAT to VDD.

0xFE

FPSM

PSM Interrupt Flag. Set when an enabled PSM interrupt condition occurs.

0xFD

FSAG

Voltage SAG Interrupt Flag. Set when an ADE energy measurement SAG condition occurs.

0xFC

RESERVED

This bit must be kept cleared for proper operation.

0xFB

FVADC

VDCIN Monitor Interrupt Flag. Set when VDCIN changes by VDCIN_DIFF or when VDCIN

measurement is ready.

0xFA

FBAT

VBAT Monitor Interrupt Flag. Set when VBAT falls below BATVTH or when VBAT measurement is ready.

0xF9

FBSO

Battery Switchover Interrupt Flag. Set when VSWOUT switches from VDD to VBAT.

0xF8

FVDCIN

VDCIN Monitor Interrupt Flag. Set when VDCIN falls below 1.2 V.

Table 18. Battery Switchover Configuration SFR (BATPR, 0xF5)

Bit

Mnemonic

Default

Description

7 to 2

Reserved

These bits must be kept to 0 for proper operation.

Control Bits for Battery Switchover.

BATPRG[1:0]

Result

Battery switchover enabled on low VDD

Battery switchover enabled on low VDD and low VDCIN

1 to 0

BATPRG[1:0]

Battery switchover disabled

Table 19. Peripheral Configuration SFR (PERIPH, 0xF4)

Bit

Mnemonic

Default

Description

RXFLAG

If set, indicates that an Rx edge event triggered wake-up from PSM2.

VSWSOURCE

Indicates the power supply that is internally connected to VSWOUT (0 VSWOUT = VBAT, 1 VSWOUT = VDD).

VDD_OK

If set, indicates that VDD power supply is ready for operation.

PLL_FLT

If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (see Table 50) in

the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the fault and clear the PLL_FLT bit.

REF_BAT_EN

Set this bit to enable internal voltage reference in PSM2 mode. This bit should be set if LCD is on in

PSM2 mode.

Reserved

This bit should be kept to zero.

Controls the function of the P1.0/RxD pin.

RXPROG[1:0]

Result

GPIO

RxD with wake-up disabled

1 to 0

RXPROG[1:0]

RxD with wake-up enabled

Table 20. Power Management Interrupt Enable SFR (IPSME, 0xEC)

Bit

Interrupt Enable Bit

Default

Description

EPSR

Enables a PSM interrupt when the power supply restored flag (FPSR) is set.

RESERVED

Reserved.

ESAG

Enables a PSM interrupt when the voltage SAG flag (FSAG) is set.

RESERVED

This bit must be kept cleared for proper operation.

EVADC

Enables a PSM interrupt when the VADC monitor flag (FVADC) is set.

EBAT

Enables a PSM interrupt when the VBAT monitor flag (FBAT) is set.

EBSO

Enables a PSM interrupt when the battery switchover flag (FBSO) is set.

EVDCIN

Enables a PSM interrupt when the VDCIN monitor flag (FVDCIN) is set.

Table 21. Scratch Pad 1 SFR (SCRATCH1, 0xFB)

Bit

Mnemonic

Default

Description

7 to 0

SCRATCH1

Value can be written/read in this register. This value is maintained in all the power saving modes.

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