TSC2004 datasheet(31/62 Pages) TI2

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ReadCycle:Sequential,fromRegisterAddressmh

to(m+n)h

(2)

(3)

I C

Read-AddressingByte

START

I C

SlaveAddress

DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte)

DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte)

DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte)

NACK

STOP

(1)

FromMastertoSlave

A=Acknowledge(SDALOW)

N=NotAcknowledge(SDAHIGH)

S=STARTCondition

P=STOPCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

NOTES: (1)Inordertostartthenextsequence,aSTOPconditionmustbefollowedbyaSTARTcondition.IfnoSTOPis

used,thenaRepeatedSTARTmustbeused.AlsonotethatisaSTOPconditionisissuedinHigh-Speed

mode,themodewillreverttothepreviousmode:FastorStandard.

(2)mhisahexadecimalnumber.

(3)If(m+n)hisgreaterthanFh,then(m+n)hismodulo16.

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

Data access begins with the master issuing a START (or repeated START) condition followed by the 7-bit

address and a read bit (R/W = 1; see Table 5). When the eighth bit has been received and the address matches,

the slave issues an acknowledge by pulling SDA low for one clock cycle (ACK = 0). The first byte of serial data

then follows. After the first byte has been sent by the slave, it releases the SDA line for the master to issue an

acknowledge (ACK = 0). The slave issues the second byte of serial data upon receiving the acknowledgement

from the master (D7-D0), followed by a not-acknowledge bit (ACK = 1) from the master to indicate that the last

data byte has been received. The master then issues a STOP condition (P) or repeated START (Sr), which ends

the read cycle, as shown in Figure 36 and Figure 37. If the master issues a not-acknowledge (ACK = 1) after

receipt of the first data byte, the master must then issue a stop condition (P) to reset the registers. If the master

is not ready to receive the second data byte, it should issue the acknowledge (ACK = 0), or the master should

stretch the clock. Upon restart of the clock, the second byte of data can be received by the master.

Figure 36. Sequential Read Cycle

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