NRF51822-CDAC-R datasheet(6/130 Pages) NORDIC

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Page 6

nRF51822 Product Specification v3.3

October 2013

2.0

This version of the document will target the nRF51822 QFAA G0 revision of the chip. If you

are working with a previous revision of the chip, read version 1.3 or earlier of the

document.

Updated the following sections:

Key Feature list on the front page,

Chapter 1 “Introduction” on page 10,

Section 2.1 “Block diagram” on page 11,

Section 2.2 “Pin assignments and functions” on page 12,

Section 3.2 “Memory” on page 21,

Section 3.5 “Programmable Peripheral Interconnect (PPI)” on page 27,

Section 3.7 “GPIO” on page 31,

Section 4.1 “2.4 GHz radio (RADIO)” on page 32,

Section 4.2 “Timer/counters (TIMER)” on page 33,

Section 4.3 “Real Time Counter (RTC)” on page 33,

Section 4.10 “Serial Peripheral Interface (SPI/SPIS)” on page 35,

Section 4.12 “Universal Asynchronous Receiver/Transmitter (UART)” on page 36,

Section 4.14 “Analog to Digital Converter (ADC)” on page 36,

Section 4.15 “GPIO Task Event blocks (GPIOTE)” on page 36,

Chapter 5 “Instance table” on page 37,

Chapter 6 “Absolute maximum ratings” on page 38,

Chapter 8 “Electrical specifications” on page 40,

Section 8.1 “Clock sources” on page 40,

Section 8.1.2 “16 MHz crystal oscillator (16M XOSC)” on page 41,

Section 8.1.3 “32 MHz crystal oscillator (32M XOSC)” on page 42,

Section 8.2 “Power management” on page 45,

Section 8.3 “Block resource requirements” on page 49,

Section 8.7 “Universal Asynchronous Receiver/Transmitter (UART) specifications” on

page 56,

Section 8.9 “Serial Peripheral Interface (SPI) Master specifications” on page 58,

Section 8.11 “GPIO Tasks and Events (GPIOTE) specifications” on page 60,

Section 8.13 “Timer (TIMER) specifications” on page 62,

Section 8.16 “Random Number Generator (RNG) specifications” on page 63,

Section 8.17 “AES Electronic Codebook Mode Encryption (ECB) specifications” on page 63,

Section 8.18 “AES CCM Mode Encryption (CCM) specifications” on page 63,

Section 8.19 “Accelerated Address Resolver (AAR) specifications” on page 63,

Section 8.21 “Quadrature Decoder (QDEC) specifications” on page 64,

Section 11.1 “PCB guidelines” on page 79,

Section 11.3 “QFAA QFN48 package” on page 82, and

Section 11.7 “CEAA WLCSP package” on page 106.

Added the following sections:

Section 3.3 “Memory Protection Unit (MPU)” on page 23,

Section 4.5 “AES CCM Mode Encryption (CCM)” on page 34,

Section 4.6 “Accelerated Address Resolver (AAR)” on page 34,

Section 4.16 “Low Power Comparator (LPCOMP)” on page 36,

Section 8.5.7 “Antenna matching network requirements” on page 55,

Section 8.8 “Serial Peripheral Interface Slave (SPIS) specifications” on page 57,

Section 8.18 “AES CCM Mode Encryption (CCM) specifications” on page 63,

Section 8.19 “Accelerated Address Resolver (AAR) specifications” on page 63, and

Section 8.24 “Low Power Comparator (LPCOMP) specifications” on page 66.

May 2013

1.3

Updated schematics and BOMs in section 11.3 on page 61.

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