UCD3138128PFCG4.A datasheet(38/84 Pages) TI2

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Digital Comparator 0

Control

Digital Comparator 1

Control

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Control

Digital Comparator 3

Control

Front End

Control 0

Front End

Control 1

Front End

Control 2

Analog

Comparator 0

Analog Comparator 0

Control

Analog

Comparator 1

Analog Comparator 1

Control

Analog

Comparator 2

Analog Comparator 2

Control

Analog

Comparator 3

Analog Comparator 3

Control

Analog

Comparator 4

Analog Comparator 4

Control

Analog

Comparator 5

Analog Comparator 5

Control

Analog

Comparator 6

Analog Comparator 6

Control

External GPIO

Detection

fault[2:0]

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DPWM 1

DPWM 2

DPWM 3

DPWM 0

Fault Control

DPWM 1

Fault Control

DPWM 2

Fault Control

DPWM 3

Fault Control

Analog Comparator

Automated Ramp

DCM Detection

HFO/LFO

Fail Detect

UCD3138128, UCD3138A64

SLUSBZ8B – JUNE 2014 – REVISED FEBRUARY 2017

www.ti.com

Product Folder Links: UCD3138128 UCD3138A64

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Figure 23. Fault Mux Block Diagram

9.3.6 Communication Ports

9.3.6.1 SCI (UART) Serial Communication Interface

maximum

two

independent

Serial

Communication

Interface

(SCI)

Universal

Asynchronous

Receiver/Transmitter (UART) interfaces are included within the device for asynchronous start-stop serial data

communication (see the pin out sections for details). Each interface has a 24 bit pre-scaler for supporting

programmable baud rates, a programmable data word and stop bit options. Half or full duplex operation is

configurable through register bits. A loop back feature can also be setup for firmware verification. Both SCI-TX

and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being used.

9.3.6.2 PMBUS/I2C

The UCD3138x has two independent interfaces which both support PMBus and I2C in master and slave modes.

Only one of the interfaces has control of the address pin current sources as well as support for the optional

Control and Alert lines described in the PMBus specification. Other than these differences, the interfaces are

identical.

The PMBus/I2C interface is designed to minimize the processor overhead required for interface. It can

automatically detect and acknowledge addresses. It handles start and stop conditions automatically, and can

clock stretch until the processor has time to poll the PMBus status. It will automatically receive and send up to 4

bytes at a time. It can automatically verify and generate a PEC. This means that a write byte command can be

received by the processor with only one function call. There is no need for any interrupts at all with this

PMBus/I2C interface. If it is polled every few milliseconds, it will work perfectly.

The interface also supports automatic ACK of two independent addresses. If both PMBus/I2C interfaces are used

at the same time a total of 4 independent addresses can be automatically detected.

Example: PMBus Address Decode via ADC12 Reading

The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address decoding.

At power-up the device applies IBIAS to each address detect pin and the voltage on that pin is captured by the

internal 12-bit ADC.

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