UCD3138128PFC.A datasheet(24/84 Pages) TI2

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EAP0

EAN0

DAC0

EADC

4 bit dithering gives 14 bits of effective resolution

97.65625 V/LSB effective resolution

6 bit ADC

8mV/LSB

Signed 9 bit result

(error) 1 mV /LSB

AFE_GAIN

10 bit DAC

1.5625mV/LSB

Value

Dither

CPCC

Filter x

Ramp

SAR/Prebias

Absolute Value

Calculation

Averaging

10 bit result

1.5625mV/LSB

3-AFE_GAIN

Peak Current Mode

Comparator

Peak Current

Detected

AFE_GAIN

UCD3138128, UCD3138A64

SLUSBZ8B – JUNE 2014 – REVISED FEBRUARY 2017

www.ti.com

Product Folder Links: UCD3138128 UCD3138A64

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Figure 10. Front End Module

9.3.2.1.2

DPWM Module

The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple

DPWM modules within the UCD3138x system can be configured to support all key power topologies. DPWM

modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It

can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to

control power supply outputs with multiphase or interleaved DPWM configurations.

The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width

modulated outputs for the power stage switches. The filter calculates the necessary duty ratio as a 24-bit number

in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This

duty ratio value is used to generate the corresponding DPWM output ON time. The resolution of the DPWM ON

time is 250 psec.

Each DPWM module can be synchronized to another module or to an external synchronization signal. An input

SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM

modules—occur when the ramp timer crosses a programmed threshold. This allows the phase of the DPWM

outputs for multiple power stages to be tightly controlled.

The DPWM logic takes the output of the filter and converts it into the correct DPWM output for several power

supply topologies. It provides for programmable dead times and cycle adjustments for current balancing between

phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can

provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to several

fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers. Fault

handling is covered in the Fault Mux section.

Each DPWM module supports the following features:

•

Dedicated 14 bit time-base with period and frequency control

•

Shadow period register for end of period updates.

•

Quad-event control registers (A and B, rising and falling) (Events 1-4)

–

Used for on/off DPWM duty ratio updates.

•

Phase control relative to other DPWM modules

•

Sample trigger placement for output voltage sensing at any point during the DPWM cycle.

•

Support for 2 independent edge placement DPWM outputs (same frequency or period setting)

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