UCD3138064ARGCTG4.A datasheet(20/84 Pages) TI2

Nome de Peças	UCD3138064ARGCTG4.A

Descrição Electrónicos	UCD3138064A Highly Integrated Digital Controller for Isolated Power

PDF	84 Pages

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Fabricante Electrônico	TI2 [Texas Instruments]

Página de início	https://www.ti.com

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DPWM

ADC12

Front-end Control

Peak Current

Mode

Timer

Filter

Constant

Power/Constant

Current

SCI

GIO

Module

C001

UCD3138064A

SLUSCA5B – DECEMBER 2015 – REVISED JANUARY 2017

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Specifications

Figure 5-10. Clock Gating Power Savings

The power disable control register provides control bits that can enable or disable the clock to several

peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.

By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be

disabled in order to block the propagation of the clock signal to that peripheral and therefore reduce the

overall current consumption of the device. The power savings chart displays the power savings per

module. For example there are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be

saved.

UCD3138064ARGCTG4.A Folha de dados(PDF) 20 Page - Texas Instruments