UCD3138 datasheet(72/99 Pages) TI2

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12 Layout

12.1 Layout Guidelines

12.1.1 EMI and EMC Mitigation Guidelines

Every design is different in terms of EMI and EMC mitigation, and all designs require their own solution.

• Apply multiple different capacitors for different frequency range on decoupling circuits. Each capacitor has

different ESL, capacitance and ESR, and different frequency responses.

• Avoid long traces close to radiation sources, and place them into an internal layer. It is preferred to have

ground shielding and add a termination circuit at the end of the trace.

• TI recommends single ground: SGND. A multilayer such as 4 layers board is recommended so that one solid

SGND is dedicated for return current path.

– Use one whole layer (L2) for SGND plane as shown in Figure 12-1. Use many vias (such as 9 vias) to

connect the extended power pad to the internal SGND plane layer. It is preferred to have the vias close to

AGND pins and DGND pins of the device.

Figure 12-1. Optional Ground Layer Assignment

• Add LPF on analog signals close to the header connecting the control card and the power board.

• Do not use a ferrite bead to connect V33A and V33D instead of using 1-Ω resistor.

• Avoid negative current and negative voltage on all pins. Schottky diodes may be needed to clamp the

voltage; avoid the voltage spike on all pins to exceed 3.8 V or below –0.3 V; add Schottky diodes on the pins

which could have voltage spikes during surge test; be aware that Schottky diode has relatively higher leakage

current, which can affect the voltage sensing at high temperatures. The need for external Schottky diodes is

conditional. For example, the DPWM pins only need external Schottky diodes when there is a long distance,

for example, more than 3 inches, between the control card and main power stage because in this case, the

trace can pick up noise and cause electrical overstress on the device pins. The same is true for GPIO and

PMBus pins.

• The auxiliary supply is normally a flyback converter, and its power transformer can generate a large

electromagnetic field which can interfere with other electronic circuitry. By shielding the primary side windings,

the EMI can be effectively reduced so that the surrounding circuits can have a quieter working environment.

12.1.2 BP18 Pin

Two parallel capacitors, 1µF and 10nF, are used between BP18 and SGND. The 10nF is placed closer to the

pin than 1uF. Please note that only for the UCD3138 (40-pin and 64-pin) and UCD3138064 (40-pin and 64-pin)

devices, it is required to have a 2.2-µF decoupling capacitor between V33D to BP18. The 2.2-µF capacitor is

required to ramp BP18 when V33D is ramping up. Place the capacitors close to the device pins, and keep the

return loop as small as possible.

12.1.3 Additional Bias Guidelines

• Apply multiple different capacitors for different frequency range on decoupling circuits. Each capacitor has

different ESL, capacitance, ESR and different frequency response.

UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

www.ti.com

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