L99LD01 datasheet(34/69 Pages) STMICROELECTRONICS

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SPI functional description

L99LD01

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DocID025319 Rev 3

3.3.3

Operating code definition

The SPI interface features four different addressing modes which are listed in Table 10.

The <Write Mode> and <Read Mode> operations allow access to the RAM of the device.

A <Read and Clear Mode> operation is used to read a status register and subsequently

clears its content.

The <Read Device Information> allows access to the ROM area which contains device

related information such as <ID-Header>, <Product Code>, <Silicon Version> and <SPI-

frame-ID>.

Write mode

The write mode of the device allows writing the content of the input data byte into the

addressed register. Incoming data are sampled on the rising edge of the serial clock (SCK),

MSB first.

Table 8. Global status byte

Bit

Name

Description

Global Error

Flag (GEF)

This bit is an OR combination of the remaining bits of the register OR (Vs_uv) OR

(Lmode_err)

Comm_Err

The right number of SPI clocks within any valid spi command is 24.

If not, then this bit is set to ‘1’.

This bit goes to ‘0’ automatically after any valid spi command

Not (Chip reset

OR Comm Err)

After a POR phase this bit is active (‘0’).

It becomes inactive (‘1’) after the first valid spi command,

provided that any communication error occurs.

LED Overload

This bit is set when an LED overcurrent event is detected

Temp. warning

Temperature Warning for the LED

Overvoltage

LED chain overvoltage or Vs overvoltage via INP_OV

(Led_Ov OR Vs_Overvoltage)

VCC1 Error

This bit is an OR combination of all the errors related to VCC1

Fail Safe

This bit is set if the device is in a limp home mode

(Data In stuck at ‘0’ or ‘1’, watchdog time out, software limp home), VCC1 undervoltage for

more than 2 ms in active mode.

Table 9. Operation code definition

OC1

OC0

Meaning

Write operation

Read operation

Read and clear status operation

Read device information

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