Parameter

Symbo

l

Min.

Typ.

Max.

Units

Test conditions

Data delay after rising edge of CK

tD

5

20

ns

CL = 15 pF

Figure 4. Timing sequence diagram

MCLK

MDAT

tD

MCLK period

1

2

3

4

The data is provided to the MDAT output 2 clock cycles after the effective sampling instant.

Table 10. LVDS transmitter signaling specifications (ISOSD61L)

Parameter

Symbol Min.

Typ.

Max.

Units

Test Conditions

Output voltage high

VOH

-0.3

1475

mV

RLOAD = 110 Ω +/- 20%

Output voltage low

VOL

925

mV

RLOAD = 110 Ω +/- 20%

Output differential voltage

|VOD|

240

420

mV

RLOAD = 110 Ω +/- 20%

Output offset voltage

VOS

1125 1200

1275

mV

RLOAD = 110 Ω +/- 20%

Output current

IO

2.2

3.7

mA

RLOAD = 110 Ω +/- 20%

LVDS load impedance, single ended

RL

80

110

140

Ω

VCM = 1 V and 1.4 V

RL mismatch between both channels

∆RL

10

%

MDAT rise time

tLH

0.5

5

ns

RLOAD = 110 Ω +/- 20%

CLOAD = 30 pF

MDAT fall time

tHL

0.5

5

ns

RLOAD = 110 Ω +/- 20%

CLOAD = 30pF

Table 11. LVDS receiver signaling specifications

Parameter

Symbol

Min.

Typ.

Max.

Units

Conditions

Voltage range

VR

-0.3

3.6

V

RLOAD = 110 Ω +/- 20%

Common mode voltage(1)

VC

0.05

2.4(2)

V

RLOAD = 110 Ω +/- 20%

Differential input voltage(3)

|Vi|

100

mV

RLOAD = 110 Ω +/- 20%

Differential input hysteresis voltage(4)

|VHYS|

25

mV

RLOAD = 110 Ω +/- 20%

Differential input capacitance

Ci

5

pF

RLOAD = 110 Ω +/- 20%

Bias resistors(5)

RPULLUP/

PULLDOWN

140

200

260

k Ω

1. Vc is defined as the voltage that is mid-way between VH and VL.

2. This parameter is guaranteed with Vdd > 4 V.

3. |Vi| defines the minimum differential voltage that is guaranteed to be recognized as a valid input, 1 or 0, by the receiver.

ISOSD61

Device specifications

DS13605 - Rev 11

page 8/23