ISOSD61 datasheet(7/23 Pages) STMICROELECTRONICS

7 / 23 page

Parameter

Symbol

Min.

Typ.

Max.

Units

Test conditions

Differential nonlinearity

DNL

±0.2

LSB

No missing codes

Offset error

VVOS

-0.8

Offset drift vs. temperature

TCVVOS

1.5

4.5

µV/°C

Offset drift vs. VDDISO

200

µV/V

Gain error

±1.0

Gain error drift vs.

Temperature

TCGE

ppm/°C

Gain error drift vs. VDDISO

600

µV/V

ANALOG INPUTS

Full-scale differential voltage input

range

FSR

-320

+320

VIN = VIN+ - VIN-

Average input bias current

IINA

–0.5

µA

VDDISO = 5V, VDD = 5V, VIN+ = 0 V;

IINA

µA

VDDISO = 5 V, VDD = 5 V, VIN+ = 300

mV;

Input capacitance

CINA

Across VIN+ or VIN- to GNDISO

DYNAMIC CHARACTERISTICS

Signal-to-noise ratio

SNR

VIN+=-200 mV to +200 mV

fMCLKIN = 5 to 15 MHz

VIN+=-250 mV to +250 mV

fMCLKIN = 20 MHz

Signal-to-(noise + distortion) ratio

SNDR

Effective number of bits

ENOB

bits

Spurious free dynamic Range

SFDR

Total harmonic distortion

THD

-83

Common-mode transient immunity(1)

CMTI

kV/µs

Transient Pulse repetition frequency

up to 100 KHz

POWER SUPPLY

VDDISO supply current

IDDISO

@ 25 MHz

@ 10 MHz

VDD supply current

IDD

VDD = 5 V,

fMCLKIN = 25 MHz

VDD = 5 V,

fMCLKIN = 10 MHz

12.5

VDD = 3.3 V,

fMCLKIN = 25 MHz

10.5

VDD = 3.3 V,

fMCLKIN = 10 MHz

1. Guaranteed by characterization

Table 9. Timing specifications

Parameter

Symbo

Min.

Typ.

Max.

Units

Test conditions

Modulator clock input frequency

fCK

MHz

Clock duty cycle 48% to 52%

ISOSD61

Device specifications

DS13605 - Rev 11

page 7/23

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