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PTHXX050

(Top View)

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PTH03050Y

PTH05050Y

PTH12050Y

SLTS221A–MARCH 2004–REVISED OCTOBER 2005

Terminal Functions

TERMINAL

DESCRIPTION

NAME

NO.

VIN

3

The positive input voltage power node to the module, which is referenced to common GND.

This is the common ground connection for the VIN and VTT power connections. It is also the 0-VDC reference for

GND

1

the control inputs.

The module senses the voltage at this input to regulate the output voltage, VTT. The voltage at VREF is also the

reference voltage for the system bus receiver comparators. It is normally set to precisely half the bus driver supply

VREF

2

voltage (VDDQ÷ 2), using a resistor divider. The Thevenin impedance of the network driving the VREF pin should

not exceed 500 Ω. See the Typical DDR Application Diagram in the Application Information section for reference.

This is the regulated power output from the module with respect to the GND node, and the tracking termination

supply for the application data and address buses. It is precisely regulated to the voltage applied to the module's

VTT

6

VREF input, and is active active about 20 ms after a valid input source is applied to the module. Once active it will

track the voltage applied at VREF.

The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low-level

ground signal to this input turns off the output voltage, VTT. Although the module is inhibited, a voltage, VDDQ will

be present at the output terminals, fed through the DDR memory. When the Inhibit is active, the input current

Inhibit

4

drawn by the regulator is significantly reduced. If the Inhibit pin is left open circuit, the module will produce an

output whenever a valid input source is applied. See the Typical DDR Application Diagram in the Application

Information section for reference.

N/C

5

No Connection

4