LP55231 datasheet(7/59 Pages) TI2

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LP55231

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SNOSCR5D – MARCH 2013 – REVISED DECEMBER 2016

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(1)

Specification is verified by design and is not tested in production. VEN = 1.65 V to VDD.

(2)

The ideal external clock signal for the LP55231 is a 0-V to VEN 25% to 75% duty-cycle square wave. At frequencies above 32.7 kHz,

program execution is faster, and at frequencies below 32.7 kHz program execution is slower.

6.10 Recommended External Clock Source Conditions

See

(1) (2)

MIN

NOM

MAX

UNIT

LOGIC INPUT CLK

ƒCLK

Clock frequency

32.7

kHz

tCLKH

High time

µs

tCLKL

Low time

µs

Clock rise time

10% to 90%

µs

Clock fall time

90% to 10%

µs

(1)

Specification is verified by design and is not tested in production. VEN = 1.65 V to VDD.

6.11 Serial Bus Timing Parameters (SDA, SCL)

See

(1) and Figure 2

MIN

MAX

UNIT

ƒSCL

Clock frequency

400

kHz

Hold time (repeated) START condition

0.6

µs

Clock low time

1.3

µs

Clock high time

600

Setup time for a repeated START condition

600

Data hold time

Data setup time

100

Rise time of SDA and SCL

20 + 0.1 Cb

300

Fall time of SDA and SCL

15 + 0.1 Cb

300

Setup time for STOP condition

600

Bus free time between a STOP and a START condition

1.3

µs

Capacitive load parameter for each bus line

Load of 1 pF corresponds to one nanosecond.

200

Figure 1. External Clock Signal

Figure 2. Timing Parameters

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