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EXAMPLE BOARD LAYOUT

(5.4)

(1.3) TYP

(

0.2) TYP

VIA

(R0.05) TYP

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

8X (1.55)

8X (0.6)

6X (1.27)

(2.95)

NOTE 9

(4.9)

NOTE 9

(2.71)

(3.4)

SOLDER MASK

OPENING

(1.3)

TYP

4214849/B 09/2025

PowerPAD

SOIC - 1.7 mm max height

DDA0008B

PLASTIC SMALL OUTLINE

SYMM

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

SCALE:10X

1

4

5

8

SOLDER MASK

OPENING

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

9

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

TM

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-8

OPENING

SOLDER MASK

METAL UNDER

SOLDER MASK

SOLDER MASK

DEFINED