SPSB100PTR datasheet(64/213 Pages) STMICROELECTRONICS

64 / 213 page

<WD Type 1> indicates the Long open window duration. On this byte, bits 5 and 4 are zero and bits 3 to 0 come

from LOW_SET(3-0) user NVM bits. Refer to the Table 32 describing the long open window durations according

to LOW_SET(3-0) from user NVM.

<WD Type 2> describes the default timing of the window watchdog.

The binary value of CW[2:0] times 5 ms defines the typical closed window time (tCW) and OW[2:0] times 5 ms

defines the typical open window time (tOW). See the Figure 37 with tCW = TEFW and tOW = TLFW - TEFW.

Figure 37. Window watchdog operation

tLOW

tCW

tOW

tCW

tOW

tCW

tOW

tLOW

tCW

tLOW

tOWF

WD-

Tigger

normal

operation

missing

trigger

early

write

time

= correct trigger timing

= early trigger timing

= missing trigger

tCW = closed window (early failure window)

tLOW = long open window

tOW = open window (late failure window - early failure window)

= tCW + tOW = open window fail

tOWF

NRST

The watchdog trigger bit location is defined by the <WD bit pos. X> registers.

Table 18. WD bit position

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WD bit pos 1

Defines the register addresses of the WD trigger bit(s)

WD bit pos 2

Defines the binary bit position

<WD bit pos 1>: 44H; watchdog trigger bit located at address 04H (DCR4)

<WD bit pos 2>: C0H; watchdog trigger bit location is bit0

<WD bit pos 3>: 00H

5.2.3.3

Device application registers (RAM)

The device application registers are all registers accessible using OpCode ‘00’, ‘01’ and ‘10’.

SPSB100

Serial peripheral interface (SPI)

DS14640 - Rev 2

page 64/213

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