9

10

SDATA

SCLK

SMBHost

CDC706

CBUS

CBUS

RP

RP

Not Recommended for New Designs

CDC706

www.ti.com...................................................................................................................................... SCAS829B – SEPTEMBER 2006 – REVISED FEBRUARY 2008

SMBus Hardware Interface

The following diagram shows how the CDC706 clock synthesizer is connected to the SMBus. Note that the

current through the pullup resistors (Rp) must meet the SMBus specifications (min 100 μA, max 350 μA). If the

CDC706 is not connected to SMBus, the SDATA and SCLK inputs have to be connected with 10 k

Ω resistors to

VCC to avoid floating input conditions.

Figure 12. SMBus Hardware Interface

Copyright © 2006–2008, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Link(s): CDC706