www.ti.com

EXAMPLE BOARD LAYOUT

12X (0.65)

(0.83)

(0.83)

(R0.05) TYP

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

16X (0.75)

16X (0.305)

(3.65)

(3.65)

(

2.16)

(

0.2) TYP

VIA

VQFN - 1 mm max height

RGV0016A

PLASTIC QUAD FLATPACK - NO LEAD

4219037/A 06/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SYMM

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

SEE SOLDER MASK

DETAIL

1

4

5

8

9

12

13

16

17

METAL EDGE

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

SOLDER MASK

OPENING

EXPOSED

METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DEFINED

SOLDER MASK DETAILS