©1988 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74AC109, 74ACT109 Rev. 1.5

2

Logic Symbols

Truth Table

Each half.

H

= HIGH Voltage Level

L

= LOW Voltage Level

= LOW-to-HIGH Transition

X

= Immaterial

Q0(Q0) = Previous Q0(Q0) before LOW-to-HIGH Transition of Clock

Logic Diagram

One half shown.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

Inputs

Outputs

SD

CD

CP

J

K

Q

Q

LH

X

X

X

H

L

HL

X

X

X

L

H

LL

X

X

X

H

H

HH

L

L

L

H

HH

HL

Toggle

HH

L

H

Q0

Q0

HH

H

H

H

L

HH

L

X

X

Q0

Q0

IEEE/IEC