STM32MP151AAA3 datasheet(34/245 Pages) STMICROELECTRONICS

34 / 245 page

Functional overview

STM32MP151A

34/245

DS12500 Rev 1

3.15

DMA controllers

The devices features three DMA modules to unload CPU activity:

•

A master direct memory access (MDMA)

The MDMA is a high-speed DMA controller, which is in charge of all types of memory

transfers (peripheral to memory, memory to memory, memory to peripheral), without

any CPU action. It features a master AXI interface.

The MDMA is located in MPU domain. It is able to interface with the other DMA

controllers located in MCU domain to extend the standard DMA capabilities, or can

manage peripheral DMA requests directly.

Each of the 32 channels can perform block transfers, repeated block transfers and

linked list transfers.

The MDMA can be set to make secure transfers to secured memories.

•

Two DMA controllers (DMA1, DMA2), located in MCU domain. Each controller is a

dual-port AHB, for a total of 16 DMA channels to perform FIFO-based block transfers.

The DMAMUX is an extension of the DMA1 and DMA2 controllers. It multiplexes and routes

the DMA peripheral requests to the DMA1 or DMA2 controllers, with a high flexibility,

maximizing the number of DMA requests that run concurrently, as well as generating DMA

requests from peripheral output trigger or DMA event.

3.16

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-

M4 with FPU core.

•

Closely coupled NVIC gives low-latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Allows early processing of interrupts

•

Processing of late arriving, higher-priority interrupts

•

Support tail chaining

•

Processor context automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

3.17

Extended interrupt and event controller (EXTI)

The extended interrupt and event controller (EXTI) manages individual CPU and system

wakeup through configurable and direct event inputs. It provides wake-up requests to the

power control, and generates an interrupt request to the CPUs NVIC or GIC and events to

the CPUs event inputs. For each CPU an additional event generation block (EVG) is needed

to generate the CPU event signal.

The EXTI wake-up requests allow the system to be woken up from Stop mode, and the

CPUs to be woken up from CStop and CStandby modes.

The interrupt request and event request generation can also be used in Run mode.

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