ADL5375

Rev. 0 | Page 8 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADL5375

TOP VIEW

(Not to Scale)

DSOP

LOIP

COMM

LOIN

COMM

NC

VPS1

RFOUT

COMM

NC

COMM

NC

1

3

2

4

5

6

18

16

17

15

14

13

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

DSOP

Output Disable. A logic high on this pin disables the RF output. Connect this pin to ground or leave it

floating to enable the output.

2, 5, 8, 11, 12,

14, 17, 19, 20, 23

COMM

Input Common Pins. Connect to the ground plane via a low impedance path.

3, 4

LOIP, LOIN

Local Oscillator Inputs.

Single-ended operation: The LOIP pin is driven from the LO source through an ac-coupling capacitor

while the LOIN pin is ac-coupled to ground through a capacitor.

Differential operation: The LOIP and LOIN pins must be driven differentially through ac-coupling

capacitors in this mode of operation.

6, 7, 13, 15,

NC

No Connect. These pins can be left open or tied to ground.

9, 10, 21, 22

QBBN, QBBP,

IBBP, IBBN

Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs should be

dc-biased to the recommended level depending on the version.

ADL5375-05: 500 mV

ADL5375-15: 1500 mV

These inputs should be driven from a low impedance source. Nominal characterized ac signal swing is

500 mV p-p on each pin. This results in a differential drive of 1 V p-p. These inputs are not self-biased

and have to be externally biased.

16

RFOUT

RF Output. Single-ended, 50 Ω internally biased RF output. RFOUT must be ac-coupled to the load.

18, 24

VPS1, VPS2

external bypassing, connect 0.1 μF and 1000 pF capacitors between each pin and ground.

EP

Exposed Paddle. Connect to the ground plan via a low impedance path.