TMP103

SCL

V+

SDA

GND

Diode Temp.

Sensor

Control Logic

A/D

Converter

Serial

Interface

Oscillator

Registers

Temperature

TMP103

0.01mF

V+

GND

2

5

1

SCL

6

SDA

To

Two-Wire

Controller

10

TMP103

SBOS545D – FEBRUARY 2011 – REVISED DECEMBER 2018

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7 Detailed Description

7.1 Overview

The TMP103 is a digital output temperature sensor in a wafer chip-scale package (WCSP) that is optimal for

thermal management and thermal profiling. The TMP103 includes a two-wire interface that is compatible with

both I2C and SMBus interfaces. In addition, the TMP103 has the capability of executing multiple device access

(MDA) commands that allow multiple TMP103 devices to respond to a single global bus command. MDA

commands reduce communication time and power in a bus that contains multiple TMP103 devices. The TMP103

is specified over a temperature range of –40ºC to 125ºC.

The TMP103 serial interface is designed to support up to eight TMP103 devices on a single bus. The TMP103 is

offered with eight internal interface addresses. Each unique address option can be used as a location or

temperature zone designator. The TMP103 responds to standard I2C and SMBus slave protocols that allow the

internal registers to be written to or read from on an individual basis. The TMP103 also responds to MDA

commands that allow all the devices on the bus to be written to or read from, without having to send the

individual address and commands to each device.

Pullup resistors are required on SCL and SDA. TI also recommends a 0.01-μF bypass capacitor, as shown in

Figure 11.

NOTE: SCL and SDA pins require pullup resistors.

Figure 11. Typical Connections

The temperature sensor in the TMP103 is the chip itself. Thermal paths run through the package bumps as well

as the package. The lower thermal resistance of metal causes the bumps to provide the primary thermal path.

To maintain accuracy in applications that require air or surface temperature measurement, take care to isolate

the package from ambient air temperature.

7.2 Functional Block Diagram