STM32F429NET7 datasheet(140/231 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F427xx STM32F429xx

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SPI interface characteristics

Unless otherwise specified, the parameters given in Table 62 for the SPI interface are

derived from tests performed under the ambient temperature, fPCLKx frequency and VDD

supply voltage conditions summarized in Table 17, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C = 30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI).

1. Guaranteed by design.

2. Spikes with widths below tAF(min) are filtered.

3. Spikes with widths above tAF(max) are not filtered

Table 62. SPI dynamic characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode, SPI1/4/5/6,

2.7 V≤VDD≤3.6 V

MHz

Slave mode,

SPI1/4/5/6,

2.7 V≤VDD≤3.6 V

Receiver

Transmitter/

full-duplex

38(2)

Master mode, SPI1/2/3/4/5/6,

1.7 V≤VDD≤3.6 V

22.5

Slave mode, SPI1/2/3/4/5/6,

1.7 V≤VDD≤3.6 V

22.5

Duty(SCK)

Duty cycle of SPI clock

frequency

Slave mode

tw(SCKH)

SCK high and low time

Master mode, SPI presc = 2,

2.7 V≤VDD≤3.6 V

TPCLK − 0.5

TPCLK

TPCLK+0.5

tw(SCKL)

Master mode, SPI presc = 2,

1.7 V≤VDD≤3.6 V

TPCLK − 2

TPCLK

TPCLK+2

tsu(NSS)

NSS setup time

Slave mode, SPI presc = 2

4TPCLK

th(NSS)

NSS hold time

Slave mode, SPI presc = 2

2TPCLK

tsu(MI)

Data input setup time

Master mode

tsu(SI)

Slave mode

th(MI)

Data input hold time

Master mode

0.5

th(SI)

Slave mode

ta(SO)

Data output access time Slave mode, SPI presc = 2

4TPCLK

tdis(SO)

Data output disable time

Slave mode, SPI1/4/5/6,

2.7 V≤VDD≤3.6 V

8.5

Slave mode, SPI1/2/3/4/5/6 and

1.7 V≤VDD≤3.6 V

16.5

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