High-Performance 48-lane, 9-port PCIe Switch

Features

PEX 8548 General Features

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48-lane PCI Express switch

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Integrated SerDes

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Up to nine configurable ports

(x1, x2, x4, x8, x16)

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37.5mm x 37.5mm,

736-ball PBGA package

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Typical Power: 4.9 Watts

PEX 8548 Key Features

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Standard Compliant

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PCI Express Base Specification, r1.1

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High Performance

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Non-blocking switch fabric

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Full line rate on all ports

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Packet Cut-Thru with 110ns max

packet latency (x16 to x16)

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Flexible Configuration

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Nine highly flexible & configurable

ports (x1, x2, x4, x8, or x16)

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Configurable with strapping pins,

EEPROM, I

2C, or Host software

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Lane and polarity reversal

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PCI Express Power Management

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Link power management states: L0,

L0s, L1, L2/L3 Ready, and L3

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Device states: D0 and D3hot

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Quality of Service (QoS)

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One Virtual Channel per port

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Eight Traffic Classes per port

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Weighted Round-Robin Ingress Port

Arbitration

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Reliability, Availability, Serviceability

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3 Standard Hot-Plug Controllers

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Upstream port as hot-plug client

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Transaction Layer end-to-end CRC

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Poison bit

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INTA# interrupt signal

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Fatal Error (FATAL_ERR#) signal

(legacy SERR equivalent)

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PCIe baseline error reporting

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Advanced Error Reporting

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Port Status bits and GPO available

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Per port error diagnostics

• Bad DLLPs

• Bad TLPs

• CRC errors

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JTAG boundary scan

Multi-purpose, High Performance ExpressLane™ Switch

The ExpressLane PEX 8548 device offers PCI Express switching capability

enabling users to add scalable high bandwidth, non-blocking interconnection

to a wide variety of applications including servers, storage systems,

communications platforms, blade servers, and embedded-control

products. The PEX 8548 is well suited for fan-out, aggregation, dual-

graphics, peer-to-peer, and fabric backplane applications.

Highly Flexible Port Configurations

The PEX 8548 offers highly configurable ports. There are a maximum of 9

ports that can be configured to any legal width from x1 to x16, in any

combination to support your specific bandwidth needs. The ports can be

configured for symmetric (each port having the same lane width and traffic

load) or asymmetric (ports having different lane widths) traffic. In the event

of asymmetric traffic, the PEX 8548 features a flexible central packet

memory that allocates a memory buffer for each port as required by the

application or endpoint. This buffer allocation along with the device's

flexible packet flow control minimizes bottlenecks when the upstream and

aggregated downstream bandwidths do not match (are asymmetric). Any of

the ports can be designated as the upstream port, which can be changed

dynamically.

High Performance

The PEX 8548 architecture supports packet cut-thru with a max latency of

110ns (x16 to x16). This, combined with large packet memory (1024 byte

maximum payload size) and non-blocking internal switch architecture,

provide full line rate on all ports for performance-hungry applications such as

storage servers or storage switch fabrics.

End-to-end Packet Integrity

The PEX 8548 provides end-to-end CRC protection (ECRC) and Poison bit

support to enable designs that require end-to-end data integrity. These

features are optional in the PCI Express specification, but PLX provides

them across its entire ExpressLane switch product line.

Configuration Flexibility

The PEX 8548 provides several ways to configure its operations. The device

can be configured through strapping pins, I

2C interface, CPU configuration

cycles, or an optional serial EEPROM. This allows for easy debug during the

development phase, performance monitoring during the operation phase, and

driver or software upgrade.

Interoperability

The PEX 8548 is designed to be fully compliant with the PCI Express Base

Specification r1.1. Additionally, it supports auto-negotiation, lane reversal,

and polarity reversal. The PEX 8548 also undergoes thorough

interoperability testing in PLX’s Interoperability Lab.

PEX 8548

Version 1.8 2008