STR910FAM32X6 datasheet(13/99 Pages) STMICROELECTRONICS

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STR91xFAx32 STR91xFAx42 STR91xFAx44

Functional overview

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3.4.2

Branch Cache (BC)

When instruction addresses are not sequential, such as a program branch situation, the

PFQ would have to flush and reload which would cause the CPU to stall if no BC were

present. Before reloading, the PFQ checks the BC to see if it contains the desired target

branch address. The BC contains up to fifteen of the most recently taken branch addresses

and the first eight instructions associated with each of these branches. This check is

extremely fast, checking all fifteen BC entries simultaneously for a branch address match

(cache hit). If there is a hit, the BC rapidly supplies the instruction and reduces the CPU

stall. This gives the PFQ time to start pre-fetching again while the CPU consumes these

eight instructions from the BC. The advantage here is that program loops (very common

with embedded control applications) run very fast if the address of the loops are contained

in the BC.

In addition, there is a 16th branch cache entry that is dedicated to the Vectored Interrupt

Controller (VIC) to further reduce interrupt latency by eliminating the stall latency typically

imposed by fetching the instruction that reads the interrupt vector address from the VIC.

3.4.3

Management of literals

Typical ARM architecture and compilers do not place literals (data constants) sequentially in

Flash memory with the instructions that use them, but instead the literals are placed at some

other address which looks like a program branch from the PFQ’s point of view. The

STR91xFA implementation of the ARM966E-S core has special circuitry to prevent flushing

the PFQ when literals are encountered in program flow to keep performance at a maximum.

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