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t − Time − 2 ms/div

Small-Signal Settling

Trigger Signal

THEORY OF OPERATION

D/A SECTION

_

+

Resistor String

VREF +

VREF −

DAC Register

VOUT

External Reference (–)

External Reference (+)

VFB

R

R

V

OUT

+ 2

V

REF* ) (VREF) * VREF*)

D

65536

(1)

RESISTOR STRING

DAC8544

SLAS420A – MAY 2004 – REVISED JUNE 2005

TYPICAL CHARACTERISTICS (continued)

This condition applies to all typical characteristics: V

REF+ = VDD, VREF– = GND, TA = 25°C (unless otherwise noted)

FULL-SCALE SETTLING TIME

(SMALL-SIGNAL NEGATIVE-GOING STEP)

Figure 29.

The architecture of the DAC8544 consists of four string DACs followed by an output buffer amplifier. Figure 30

shows a block diagram of the DAC architecture.

Figure 30. DAC8544 Architecture

The input coding to the DAC8544 is unsigned binary, which gives the ideal output voltage as:

where

• D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535.

The resistor string section is shown in Figure 31. It is simply a divide-by-two resistor, followed by a string of

resistors, each of value R. The code loaded into the DAC register determines at which node on the string the

voltage is tapped off, to be fed into the output amplifier, by closing one of the switches connecting the string to

the amplifier. Because it is a string of resistors, it is assured monotonic.

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