CC1070-RTY1 datasheet(20/57 Pages) TI2

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CC1070

SWRS043A

Page 20 of 54

Parameter

Symbol

Min

Max

Unit

Conditions

PCLK, clock

frequency

FPCLK

MHz

PCLK low

pulse

duration

TCL,min

The minimum time PCLK must be low.

PCLK high

pulse

duration

TCH,min

The minimum time PCLK must be high.

PSEL setup

time

TSS

The minimum time PSEL must be low before

positive edge of PCLK.

PSEL hold

time

THS

The minimum time PSEL must be held low after

the negative edge of PCLK.

PSEL high

time

TSH

The minimum time PSEL must be high.

PDI setup

time

TSD

The minimum time data on PDI must be ready

before the positive edge of PCLK.

PDI hold time

THD

The minimum time data must be held at PDI, after

the positive edge of PCLK.

Rise time

Trise

100

The maximum rise time for PCLK and PSEL

Fall time

Tfall

100

The maximum fall time for PCLK and PSEL

Note: The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% /

90% of VDD. The maximum load that this table is valid for is 20 pF.

Table 11. Serial interface, timing specification

9.2 Signal Interface

The

CC1070 can be used with NRZ (Non-

Return-to-Zero) data or Manchester (also

known as bi-phase-level) encoded data.

The data format is controlled by the

DATA_FORMAT[1:0] bits in the MODEM

CC1070 can be configured for three

different data formats:

Synchronous NRZ mode

During transmit operation, the

CC1070

provides the data clock at DCLK and DI is

used as data input. Data is clocked into

CC1070 at the rising edge of DCLK. The

data is modulated at RF without encoding.

See Figure 8.

Synchronous

Manchester

encoded

mode

During transmit operation, the

CC1070

provides the data clock at DCLK and DI is

used as data input. Data is clocked into

CC1070 at the rising edge of DCLK and

should be in NRZ format. The data is

modulated at RF with Manchester code.

The encoding is done by

CC1070. In this

mode the effective bit rate is half the baud

rate due to the coding. As an example,

19.2 kBaud Manchester encoded data

corresponds to a 9.6 kbps. See Figure 9.

Transparent

Asynchronous

UART

mode

During transmit operation, DI is used as

data input. The data is modulated at RF

without synchronization or encoding. In

this mode, the DCLK pin is not active and

can be set to a high or low level by

DATA_FORMAT[0]. See Figure 10.

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