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WM8994ECS/R Folha de dados(PDF) 280 Page - Cirrus Logic

Nome de Peças WM8994ECS/R
Descrição Electrónicos  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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Fabricante Electrônico  CIRRUS [Cirrus Logic]
Página de início  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8994ECS/R Folha de dados(HTML) 280 Page - Cirrus Logic

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WM8994
280
Rev 4.6
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R88 (58h) DC
Servo
Readback
9:8
DCS_CAL_COM
PLETE [1:0]
00
DC Servo Complete status
0 = DAC Write or Start-Up DC Servo mode not completed.
1 = DAC Write or Start-Up DC Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
5:4
DCS_DAC_WR
_COMPLETE
[1:0]
00
DC Servo DAC Write status
0 = DAC Write DC Servo mode not completed.
1 = DAC Write DC Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
1:0
DCS_STARTUP
_COMPLETE
[1:0]
00
DC Servo Start-Up status
0 = Start-Up DC Servo mode not completed.
1 = Start-Up DC Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
Register 58h DC Servo Readback
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R89 (59h) DC
Servo Write
Val
15:8
DCS_DAC_WR
_VAL_1 [7:0]
0000_0000
Writing to this field sets the DC Offset value for HPOUT1R
in DAC Write DC Servo mode.
Reading this field gives the current DC Offset value for
HPOUT1R.
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
7:0
DCS_DAC_WR
_VAL_0 [7:0]
0000_0000
Writing to this field sets the DC Offset value for HPOUT1L
in DAC Write DC Servo mode.
Reading this field gives the current DC Offset value for
HPOUT1L.
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
Register 59h DC Servo Write Val
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R96 (60h)
Analogue HP
(1)
7
HPOUT1L_RMV
_SHORT
0
Removes HPOUT1L short
0 = HPOUT1L short enabled
1 = HPOUT1L short removed
For normal operation, this bit should be set as the final step
of the HPOUT1L Enable sequence.
6
HPOUT1L_OUT
P
0
Enables HPOUT1L output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1 after the DC
offset cancellation has been scheduled.
5
HPOUT1L_DLY
0
Enables HPOUT1L intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1 after the



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