WM8994ECSSLASHR datasheet(206/363 Pages) CIRRUS

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WM8994

206

Rev 4.6

FREE-RUNNING FLL CLOCK

The FLL can generate a clock signal even when no external reference is available. However, it should

be noted that the accuracy of this clock is reduced, and a reference source should always be used

where possible. Note that, in free-running modes, the FLL is not sufficiently accurate for hi-fi ADC or

DAC applications. However, the free-running modes are suitable for clocking most other functions,

including the Write Sequencer, Charge Pump, DC Servo and Class D loudspeaker driver.

If an accurate reference clock is initially available, then the FLL should be configured as described

above. The FLL will continue to generate a stable output clock after the reference input is stopped or

disconnected.

If no reference clock is available at the time of starting up the FLL, then an internal clock frequency of

approximately 12MHz can be generated by implementing the following sequence:



Enable the FLL Analogue Oscillator (FLLn_OSC_ENA = 1)



Set the FOUT clock divider to divide by 8 (FLLn_OUTDIV = 000111)



Configure the oscillator frequency by setting FLLn_FRC_NCO = 1 and

FLLn_FRC_NCO_VAL = 19h

Note that the free-running FLL mode is not suitable for hi-fi CODEC applications. In the absence of

any reference clock, the FLL output is subject to a very wide tolerance; see “Electrical Characteristics”

for details of the FLL accuracy.

Note that the free-running FLL clock is selected as SYSCLK using the registers noted in Figure 67.

The free-running FLL clock may be used to support analogue functions, for which the digital audio

interface is not used, and there is no applicable Sample Rate (fs). When SYSCLK is required for

circuits such the Class D, DC Servo, Control Write Sequencer or Charge Pump, then valid Sample

Rate register settings are still required, even though the digital audio interface is not active.

For correct functionality when SYSCLK_SRC = 0, valid settings are required for AIF1_SR and

AIF1CLK_RATE. In the case where SYSCLK_SRC = 1, then valid settings are required for AIF2_SR

and AIF2CLK_RATE.

The control registers applicable to FLL free-running modes are described in Table 114.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R544 (0220h)

FLL1 Control (1)

FLL1_OSC_ENA

FLL1 Oscillator enable

0 = Disabled

1 = Enabled

(Note that this field is required for

free-running FLL1 modes only)

R548 (0224h)

FLL1 Control (5)

12:7

FLL1_FRC_NCO

_VAL [5:0]

19h

FLL1 Forced oscillator value

Valid range is 000000 to 111111

0x19h (011001) = 12MHz approx

(Note that this field is required for

free-running FLL modes only)

FLL1_FRC_NCO

FLL1 Forced control select

0 = Normal

1 = FLL1 oscillator controlled by

FLL1_FRC_NCO_VAL

(Note that this field is required for

free-running FLL modes only)

R576 (0240h)

FLL2 Control (1)

FLL2_OSC_ENA

FLL2 Oscillator enable

0 = Disabled

1 = Enabled

(Note that this field is required for

free-running FLL2 modes only)

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