WM8994ECSSLASHR datasheet(197/363 Pages) CIRRUS

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WM8994

Rev 4.6

197

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:0

AIF2CLK_RAT

0011

Selects the AIF2CLK / fs ratio

0000 = Reserved

0001 = 128

0010 = 192

0011 = 256

0100 = 384

0101 = 512

0110 = 768

0111 = 1024

1000 = 1408

1001 = 1536

All other codes = Reserved

Table 108 AIF2 Clocking Configuration

MISCELLANEOUS CLOCK CONTROLS

SYSCLK provides clocking for many of the WM8994 functions. SYSCLK clock is required to support

DSP Core functions and also the Charge Pump, Class D switching amplifier, DC servo control,

Control Write Sequencer and other internal functions.

The SYSCLK_SRC register is used to select the SYSCLK source. The source may be AIF1CLK or

AIF2CLK. Note that the bandwidth of the digital audio mixing paths will be determined by the sample

rate of whichever AIF is selected as the SYSCLK source. When using only one audio interface, the

active interface should be selected as the SYSCLK source. For best audio performance when using

AIF1 and AIF2 simultaneously, the SYSCLK source must select the AIF with the highest sample rate

(AIFn_SR).

The AIF1 DSP processing clock is derived from SYSCLK, and enabled by AIF1DSPCLK_ENA.

The AIF2 DSP processing clock is derived from SYSCLK, and enabled by AIF2DSPCLK_ENA.

The clocking of the WM8994 ADC, DAC, digital mixer and digital microphone functions is enabled by

setting SYSDSPCLK_ENA.

See “Digital Microphone Interface” for details of the DMICCLK frequency.

Two modes of ADC / Digital Microphone operation can be selected using the ADC_OSR128 bit. This

bit is enabled by default, giving best audio performance. De-selecting this bit provides a low power

alternative setting.

A high performance mode of DAC operation can be selected by setting the DAC_OSR128 bit. When

the DAC_OSR128 bit is set, the audio performance is improved, but power consumption is also

increased.

A clock is required for the Charge Pump circuit when the ground-referenced headphone outputs

(HPOUT1L and HPOUT1R) are enabled. The Charge Pump clock is derived from SYSCLK whenever

the Charge Pump is enabled. The Charge Pump clock division is configured automatically.

A clock is required for the Class D speaker driver circuit when the speaker outputs (SPKOUTL and

SPKOUTR) are enabled. The Class D clock is derived from SYSCLK whenever these outputs are

enabled in Class D mode. The Class D clock division is configured automatically. See “Analogue

Outputs

” for details of the Class D switching frequency.

A clock output (OPCLK) derived from SYSCLK may be output on a GPIO pin. This clock is enabled by

Purpose Input/Output

” to configure a GPIO pin for this function.

A slow clock (TOCLK) is derived internally in order to control volume update timeouts when the zero-

cross option is selected. This clock is enabled by register bit TOCLK_ENA, and its frequency is

controlled by TOCLK_DIV.

A de-bounce control is provided for GPIO inputs and for other functions that may be selected as GPIO

outputs. The de-bounced clock frequency is controlled by DBCLK_DIV.

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