bq4802Y

bq4802LY

SLUS464C – AUGUST 2000 – REVISED JUNE 2002

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4

AC TEST CONDITIONS, INPUT PULSE LEVELS VI = 0 V to 3.0 V, tR = tF = 5 NS, VREF = 1.5 V

Figure 1. Output Load A

3 V

100 pF

DOUT

510

Ω

962

Ω

Figure 2. Output Load B

3 V

5 pF

DOUT

510

Ω

962

Ω

OPERATING CHARACTERISTICS

READ CYCLE (TA = TOPR, VCC = 5 V)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tRC

Read cycle time

200

ns

tAA

Address access time

Output load A

100

ns

tACS

Chip select access time

Output load A

100

ns

tOE

Output enable to output valid

Output load A

100

ns

tCLZ

Chip select to output low Z

Output load B

8

ns

tOLZ

Output enable until output low Z

Output load B

0

ns

tCHZ

Output enable until output high Z

Output load B

0

45

ns

tOHZ

Output disable until output high Z

Output load B

0

45

ns

tOH

Output hold from address change

Output load A

10

ns

READ CYCLE (TA = TOPR, VCC = 3.3 V)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tRC

Read cycle time

300

ns

tAA

Address access time

Output load A

150

ns

tACS

Chip select access time

Output load A

150

ns

tOE

Output enable to output valid

Output load A

150

ns

tCLZ

Chip select to output low Z

Output load B

15

ns

tOHL

Output enable until output low Z

Output load B

0

ns

tCLH

Output enable until output high Z

Output load B

0

60

ns

tOLZ

Output disable until output high Z

Output load B

0

60

ns

tOH

Output hold from address change

Output load A

18

ns