100MHz HCSL Clock Generator

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Detailed Description

The DS4100H is a low-jitter HCSL 100MHz clock genera-

tor. It combines an AT-cut crystal, an oscillator, and a

low-noise PLL in a 5mm by 3.2mm ceramic package.

20MHz. The device operates from a single +3.3V supply.

PLL

The PLL generates a 1.6GHz high-speed clock signal

based on the 25MHz crystal oscillator output. Clock-

divider circuit M generates the output clock by scaling

the VCO output frequency. Clock-divider circuit N

applies a scaled version of the output clock signal to

the phase/frequency detector (PFD) circuit.

Output Drivers

The DS4100H is available with HCSL output buffers.

When not needed, the output buffers can be disabled

by driving the OE input to a logic-low. OE has an inter-

nal pullup resistor so that, if OE is left open, the outputs

are enabled by default. When disabled, the output

buffer goes to a high-impedance state.

Chip Information

TRANSISTOR COUNT: 2850

SUBSTRATE CONNECTED TO GROUND

PROCESS: Bipolar SiGe

Package Information

(For the latest package outline information go to

Thermal Information

THETA-JA (°C/W)

90

PACKAGE TYPE

DOCUMENT NO.

10 LCCC

56-G5032-002