AS5040 datasheet(11/28 Pages) AMSCO

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AS5040 10-BIT PROGRAMMABLE MAGNETIC ROTARY ENCODER

Revision 1.6, 03-Oct-06

www.austriamicrosystems.com

Page 11 of 28

9.2

Incremental Mode Programming

Three different incremental output modes are available.

Mode: Md1=0 / Md0=1 sets the AS5040 in quadrature

mode.

Mode: Md1=1 / Md0=0 sets the AS5040 in step / direction

mode (see Table 1)

In both modes, the incremental resolution may be

reduced from 10 bit down to 9, 8 or 7 bit using the divider

OTP bits Div1 and Div0. (see Table 6 below ).

Mode: Md1=1 / Md0=1 sets the AS5040 in brushless DC

motor commutation mode with an additional LSB

incremental signal at pin 12 (PWM_LSB).

To allow programming of all bits, the default factory

setting is all bits = 0. This mode is equal to mode 1:0

(quadrature A/B, 1LSB index width, 256ppr).

The absolute angular output value, by default, increases

with clockwise rotation of the magnet (top view). Setting

the CCW-bit (see Figure 13) allows reversing the

indicated direction, e.g. when the magnet is placed

underneath the IC:

CCW = 0 – angular value increases clockwise;

CCW = 1 – angular value increases counterclockwise.

By default, the zero / index position pulse is one LSB

wide. It can be increased to a three LSB wide pulse by

setting the Index-bit of the OTP register.

Further programming options (commutation modes) are

available for brushless DC motor-control.

Md1 = Md0 = 1 changes the incremental output pins 3, 4

and 6 to a 3-phase commutation signal. Div1 defines the

number of pulses per revolution for either a two-pole

(Div1=0) or four-pole (Div1=1) rotor.

In addition, the LSB is available at pin 12 (the LSB signal

replaces the PWM-signal), which allows for high

rotational speed measurement of up to 10,000 rpm.

OTP-Mode-Register-Bit

Pin #

Pulses per

Revolution

Incremental

Resolution

Mode

Md1

Md0 Div1 Div0 Index

ppr

bit

Default (Mode0.0)

1LSB

quadAB-Mode1.0

1LSB

quadAB-Mode1.1

3LSBs

2x256

quadAB-Mode1.2

1LSB

quadAB-Mode1.3

3LSBs

2x128

quadAB-Mode1.4

1LSB

quadAB-Mode1.5

3LSBs

2x64

quadAB-Mode1.6

1LSB

quadAB-Mode1.7

3LSBs

PWM

10 bit

2x32

Step/Dir-Mode2.0

1LSB

Step/Dir-Mode2.1

3LSBs

512

Step/Dir -Mode2.2

1LSB

Step/Dir -Mode2.3

3LSBs

256

Step/Dir -Mode2.4

1LSB

Step/Dir -Mode2.5

3LSBs

128

Step/Dir -Mode2.6

1LSB

Step/Dir -Mode2.7

LSB

Dir

3LSBs

PWM

10 bit

Commutation-Mode3.0

Commutation-Mode3.1

U(0º)

V(120º)

W(240º)

LSB

3 x 1

Commutation-Mode3.2

Commutation-Mode3.3

U’

(0º, 180º)

V’

(60º,240º)

W’

(120º,300º) LSB

2 x 3

Table 6: One Time Programmable (OTP) register options

*Note: Div1, Div0 and Index cannot be programmed in Mode 0:0

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