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Document number: BST-BMP384-DS003-11 Revision_1.0_112020

5.3.2. SPI read

Reading is done by lowering CSB and first sending one control byte. The control bytes consist of the SPI register address (=

full register address without bit 7) and the read command (bit 7 = RW = ‘1’). After writing the control byte, one dummy byte

is sent and there after data bytes. The register address is automatically incremented. The SPI read protocol is shown in

Figure 20.

Figure 20: SPI multiple byte read

5.4.

Interface parameter specification

5.4.1. General interface parameters

The general interface parameters are given in the table below:

Table 47: interface parameters

5.4.2. I²C timings

For I²C timings, the following abbreviations are used:

•

“S&F mode” = standard and fast mode

•

“HS mode” = high speed mode

•

Cb = bus capacitance on SDA line

All other naming refers to I²C specification 2.1 (January 2000).

The I²C timing diagram is shown in

Figure 21. The corresponding values are given in Table 48.

Parameter

Symbol

Condition

Min

Typ

Max

Units

Input – low level

Vil

SCK, SDI and CSB

0.25

VDDIO

Input – high level

Vih

SCK, SDI and CSB

0.7

VDDIO

Output – low level

Vol

SDI, SDO and INT,

iol=3 mA

0.2

VDDIO

Output – high level

Voh

SDI, SDO and INT

ioh=1 mA

0.8

VDDIO

CSB Pull-up resistor

Rcsb

Internal pull-up

resistance to VDDIO

100

125

kΩ

I2C bus load capacitor

On SDI and SCK

400

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