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ST10F271 Folha de dados(PDF) 80 Page - STMicroelectronics |
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ST10F271 Folha de dados(HTML) 80 Page - STMicroelectronics |
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80 / 173 page ![]() System reset ST10F271 80/173 V18 and ground: the internal 1.8V drivers are sized to drive currents of several tens of Ampere, so the current shall be limited by the external hardware. The limit of current is imposed by power dissipation considerations (Refer to Electrical Characteristics Section). In next Figures 17 and 18 Asynchronous Power-on timing diagrams are reported, respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded FLASH module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device could enter in unpredictable states, risking also permanent damages. Figure 17. Asynchronous power-on RESET (EA = 1) RSTF P0[15:13] P0[12:2] transparent transparent P0[1:0] not t. not transparent FLARST V18 XTAL1 ... ≤ 2 TCL RST ≤ 1 ms Latching point of Port0 for system start-up configuration VDD ≥ 1 ms (for on-chip VREG stabilization) RPD IBUS-CS ≤ 1.2 ms (for resonator oscillation + PLL stabilization) ≤ 10.2 ms (for crystal oscillation + PLL stabilization) RSTIN (After Filter) ≤ 500 ns ≥ 50 ns 7 TCL 3..4 TCL (Internal) not t. not t. not t. |
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